Xilinx Virtex-5 MIG DDR2 Controller Model

For faster simulation of Verilog designs that use the Xilinx Virtex-5 MIG DDR2 controller model, we offer a functional model mig_ddr2_bfm.v which implements a sparse memory array based functional model of the Xilinx MIG ap* user interface signals. The model is intended to help run fast simulations to verify user logic that will interface to a Xilinx MIG generated DDR2 controller. The model does not implement or control the actual DDR 2 signals - it implements the "user" signals that accept/produce commands and data from/to the user logic. The following ports are actually used to provide this interface:

   input                               sys_clk_p,
   input                               sys_rst_n,

   output                              clk0_tb,
   output reg                          rst0_tb,

   output reg                          app_af_afull            = 1'b0,
   output reg                          app_wdf_afull           = 1'b0,
   output reg                          rd_data_valid           = 1'b0,
   output reg [APPDATA_WIDTH-1:0]      rd_data_fifo_out        = {APPDATA_WIDTH{1'bz}},

   input                               app_af_wren,
   input  [2:0]                        app_af_cmd,
   input  [30:0]                       app_af_addr,
   input                               app_wdf_wren,
   input  [APPDATA_WIDTH-1:0]          app_wdf_data,
   input  [(APPDATA_WIDTH/8)-1:0]      app_wdf_mask_data,

   output reg                          phy_init_done           = 1'b0 

You may download (approx. 25KB) the Verilog model here.

If you have special needs for an adaptation or port of this product, please .   We would be happy to talk with you about it.